Hi Max,
On Sat, Nov 4, 2017 at 12:45 AM, Max Filippov <jcmvb...@gmail.com> wrote:
> const16 is an opcode that shifts 16 lower bits of an address register
> to the 16 upper bits and puts its immediate operand into the lower 16
> bits. It is not controlled by an Xtensa option and doesn't have a fixed
> opcode.
>
> Signed-off-by: Max Filippov <jcmvb...@gmail.com>
> ---
> target/xtensa/translate.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
> index a84bbf3bedc3..f249e810d92c 100644
> --- a/target/xtensa/translate.c
> +++ b/target/xtensa/translate.c
> @@ -1526,6 +1526,17 @@ static void translate_clrb_expstate(DisasContext *dc,
> const uint32_t arg[],
> tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0]));
> }
>
> +static void translate_const16(DisasContext *dc, const uint32_t arg[],
> + const uint32_t par[])
> +{
> + if (gen_window_check1(dc, arg[0])) {
> + TCGv_i32 v = tcg_temp_new_i32();
> +
> + tcg_gen_shli_i32(v, cpu_R[arg[0]], 16);
> + tcg_gen_ori_i32(cpu_R[arg[0]], v, arg[1] & 0xffff);
this is missing:
tcg_temp_free_i32(v);
> + }
however I think this can be simplified in 1 instr on target supporting
deposit32:
tcg_gen_deposit_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[0]], 16, 16)
Regards,
Phil.
> +}
> +
> /* par[0]: privileged, par[1]: check memory access */
> static void translate_dcache(DisasContext *dc, const uint32_t arg[],
> const uint32_t par[])
> @@ -2742,6 +2753,9 @@ static const XtensaOpcodeOps core_ops[] = {
> .name = "clrb_expstate",
> .translate = translate_clrb_expstate,
> }, {
> + .name = "const16",
> + .translate = translate_const16,
> + }, {
> .name = "depbits",
> .translate = translate_depbits,
> }, {
> --
> 2.1.4
>
>
