QEMU's behaviour in this case is matching the hardware. We claim to model an r1p0 (based on the MIDR value we report), and for the r1p0 the A53 and A57 reported the ID_MMFR0 as 0x10101105 -- this is documented in the TRMs for that rev of the CPUs. r1p3 reports the 0x10201105 you describe, but this isn't the rev of the CPU we claim to be.
In theory we could bump the rXpX but I'm not sure there's much point unless it's causing a real problem (we'd need to check what else might have changed between the two revisions). -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1723984 Title: ID_MMFR0 has an invalid value on aarch64 cpu (A57, A53) Status in QEMU: New Bug description: The ID_MMFR0 register, accessed from aarch64 state as an invalid value: - ARM ARM v8 documentation (D7.2 General system control registers) described bits AuxReg[23:20] to be "In ARMv8-A the only permitted value is 0010" - Cortex A53 and Cortex A57 TRM describe the value to be 0x10201105, so AuxReg[23:20] is 0010 too - in QEMU target/arm/cpu64.c, the relevant value is cpu->id_mmfr0 = 0x10101105; The 1 should be changed to 2. Spotted & Tested on the following qemu revision: commit 48ae1f60d8c9a770e6da64407984d84e25253c69 Merge: 78b62d3 b867eaa Author: Peter Maydell <peter.mayd...@linaro.org> Date: Mon Oct 16 14:28:13 2017 +0100 To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1723984/+subscriptions
