On 09/22/2017 12:00 PM, Peter Maydell wrote:
> When we added support for the new SHCSR bits in v8M in commit
> 437d59c17e9 the code to support writing to the new HARDFAULTPENDED
> bit was accidentally only added for non-secure writes; the
> secure banked version of the bit should also be writable.
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
> ---
> hw/intc/armv7m_nvic.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index bd1d5d3..22d5e6e 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -1230,6 +1230,7 @@ static void nvic_writel(NVICState *s, uint32_t offset,
> uint32_t value,
if (attrs.secure) {
if banked then arch is v8M,
> s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) !=
> 0;
> s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =
> (value & (1 << 18)) != 0;
> + s->sec_vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21))
> != 0;
therefore this bit is present.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
> /* SecureFault not banked, but RAZ/WI to NS */
> s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;
> s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) !=
> 0;
>
