On 08/22/2017 08:08 AM, Peter Maydell wrote: > Make the CFSR register banked if v8M security extensions are enabled. > > Not all the bits in this register are banked: the BFSR > bits [15:8] are shared between S and NS, and we store them > in the NS copy of the register. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/cpu.h | 7 ++++++- > hw/intc/armv7m_nvic.c | 15 +++++++++++++-- > target/arm/helper.c | 18 +++++++++--------- > target/arm/machine.c | 3 ++- > 4 files changed, 30 insertions(+), 13 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
