The e1000 has compatibility code to handle big endianness which makes it
mandatory to be recompiled on different targets.
With the generic mmio endianness solution, there's no need for that anymore.
We just declare all mmio to be little endian and call it a day.
Because we don't depend on the target endianness anymore, we can also
move the driver over to Makefile.objs.
Signed-off-by: Alexander Graf <ag...@suse.de>
---
Makefile.objs | 1 +
Makefile.target | 1 -
hw/e1000.c | 11 ++---------
3 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/Makefile.objs b/Makefile.objs
index 23b17ce..37d4a10 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -215,6 +215,7 @@ hw-obj-y += msix.o msi.o
hw-obj-y += ne2000.o
hw-obj-y += eepro100.o
hw-obj-y += pcnet.o
+hw-obj-y += e1000.o
hw-obj-$(CONFIG_SMC91C111) += smc91c111.o
hw-obj-$(CONFIG_LAN9118) += lan9118.o
diff --git a/Makefile.target b/Makefile.target
index 2800f47..02a7a66 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -211,7 +211,6 @@ obj-$(CONFIG_USB_OHCI) += usb-ohci.o
# PCI network cards
obj-y += rtl8139.o
-obj-y += e1000.o
# Inter-VM PCI shared memory
obj-$(CONFIG_KVM) += ivshmem.o
diff --git a/hw/e1000.c b/hw/e1000.c
index a3795c5..0c6b433 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -857,9 +857,6 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
if (index < NWRITEOPS && macreg_writeops[index]) {
macreg_writeops[index](s, index, val);
} else if (index < NREADOPS && macreg_readops[index]) {
@@ -894,11 +891,7 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
if (index < NREADOPS && macreg_readops[index])
{
- uint32_t val = macreg_readops[index](s, index);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
- return val;
+ return macreg_readops[index](s, index);
}
DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
return 0;
@@ -1131,7 +1124,7 @@ static int pci_e1000_init(PCIDevice *pci_dev)
pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
d->mmio_index = cpu_register_io_memory(e1000_mmio_read,
- e1000_mmio_write, d, DEVICE_NATIVE_ENDIAN);
+ e1000_mmio_write, d, DEVICE_LITTLE_ENDIAN);
pci_register_bar((PCIDevice *)d, 0, PNPMMIO_SIZE,
PCI_BASE_ADDRESS_SPACE_MEMORY, e1000_mmio_map);
--
1.6.0.2
