On 22 August 2017 at 16:08, Peter Maydell <peter.mayd...@linaro.org> wrote:
> Now that MPU lookups can return different results for v8M
> when the CPU is in secure vs non-secure state, we need to
> have separate MMU indexes; add the secure counterparts
> to the existing three M profile MMU indexes.
> @@ -2206,7 +2217,11 @@ static inline int cpu_mmu_index(CPUARMState *env, bool
> ifetch)
> */
> if ((env->v7m.exception > 0 && env->v7m.exception <= 3)
> || env->v7m.faultmask) {
> - return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri);
> + mmu_idx = ARMMMUIdx_MNegPri;
> + }
Incidentally this is not exactly the right check to make when
the security extension is present, but at this point in the
series it's the best we can do (the right check requires us
to have exception banking support in the NVIC so we can
check secure HF and nonsecure HF separately); the patch to
do it right will come after the NVIC patches.
thanks
-- PMM
