On 08/02/2017 09:44 AM, Peter Maydell wrote: > The ARMv7M architecture specifies that most of the addresses in the > PPB region (which includes the NVIC, systick and system registers) > are not accessible to unprivileged accesses, which should > BusFault with a few exceptions: > * the STIR is configurably user-accessible > * the ITM (which we don't implement at all) is always > user-accessible > > Implement this by switching the register access functions > to the _with_attrs scheme that lets us distinguish user > mode accesses. > > This allows us to pull the handling of the CCR.USERSETMPEND > flag up to the level where we can make it generate a BusFault > as it should for non-permitted accesses. > > Note that until the core ARM CPU code implements turning > MEMTX_ERROR into a BusFault the registers will continue to > act as RAZ/WI to user accesses. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > hw/intc/armv7m_nvic.c | 58 > ++++++++++++++++++++++++++++++++++++--------------- > 1 file changed, 41 insertions(+), 17 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
