On Mon, Jul 24, 2017 at 04:44:00PM +0200, Cédric Le Goater wrote: > On 07/24/2017 08:35 AM, David Gibson wrote: > > On Wed, Jul 05, 2017 at 07:13:27PM +0200, Cédric Le Goater wrote: > >> The Thread Interrupt Management Area for the OS is mostly used to > >> acknowledge interrupts and set the CPPR of the CPU. > >> > >> The TIMA is mapped at the same address for each CPU. 'current_cpu' is > >> used to retrieve the targeted interrupt presenter object. > >> > >> Signed-off-by: Cédric Le Goater <c...@kaod.org> > > > > Am I right in thinking that this shoehorns the XIVE TIMA state into > > the existing XICS ICP object. That.. doesn't seem like a good idea. > > The TIMA memory region is under the XIVE object because it is > unique for the system. The lookup of the ICP is simply done using > 'current_cpu'. The TIMA state is under the ICPState, yes, but this > model does not seem incorrect to me as this state contains the > interrupt information presented to a CPU.
Yeah, that's not the point I'm making. My point is that the TIMA
state isn't really the same as xics ICP state. You're squeezing one
into the other in a pretty ugly way.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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