On 07/24/2017 02:03 PM, Pranith Kumar wrote:
+#ifndef CPU_TLB_BITS_MAX
+# define CPU_TLB_BITS_MAX 8
You should simply require each backend to define this.
+++ b/tcg/i386/tcg-target.h
@@ -162,6 +162,8 @@ extern bool have_popcnt;
# define TCG_AREG0 TCG_REG_EBP
#endif
+#define CPU_TLB_BITS_MAX 12
This is probably too much.
Exemplars:
NB_MMU_MODES = 1 moxie
NB_MMU_MODES = 2 m68k
NB_MMU_MODES = 3 alpha
NB_MMU_MODES = 7 arm
NB_MMU_MODES = 8 ppc64
sizeof(CPUArchState):
tlb bits \ modes 1 2 3 7 8
8 13856 25840 38952 92024 182576
12 198176 394480 591912 1382264 1657136
Having 1.5MB of TLB data seems excessive.
Please let's get some performance numbers for various tlb bit sizes.
How much improvement do you get if you increase the size of the victim tlb
cache?
r~
