> For this specific case, the primary problem will be the implicit memory > barriers that the i386 guest requires, but that the mips64 host does not > provide. > > For tcg/mips/, TCG_TARGET_DEFAULT_MO should be 0, because the mips > architecture > does not have any implicit memory ordering. All memory barriers are explicit > via SYNC instructions. > > For target/i386, TCG_GUEST_DEFAULT_MO is TCG_MO_ALL & ~TCG_MO_ST_LD, or > > TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST > > which means that implicit memory barriers exist between load/load, > load/store, > store/store, but not store/load. > > In order to fix this, we need to add the missing barriers to the opcode > stream. > > The simplest fix for this is to put a call > > tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC) > > at the end of gen_ldst_i32 and gen_ldst_i64. That should be good enough to > make your specific case operate correctly. > > A proper fix will involve (1) emitting those barriers only if the barrier is > not implied by the host and (2) optimizing away redundant barriers. > Thanks very much. That really helps a lot.
I'll dig deeper into that and maybe feedback some patches.
