On Wed, Jul 19, 2017 at 01:56:57PM +1000, Benjamin Herrenschmidt wrote: > On Wed, 2017-07-19 at 13:08 +1000, David Gibson wrote: > > On Wed, Jul 05, 2017 at 07:13:17PM +0200, Cédric Le Goater wrote: > > > Let's provide an empty shell for the XIVE controller model with a > > > couple of attributes for the IRQ number allocator. The latter is > > > largely inspired by OPAL which allocates IPI IRQ numbers from the > > > bottom of the IRQ number space and allocates the HW IRQ numbers from > > > the top. > > > > > > The number of IPIs is simply deduced from the max number of CPUs the > > > guest supports and we provision a arbitrary number of HW irqs. > > > > > > The XIVE object is kept private because it will hold internal tables > > > which do not need to be exposed to sPAPR. > > It does have an MMIO presence though... more than one even. There's the > TIMA (per-HW thread control area) and there's the per-interrupt MMIO > space which are exposed to the guest. There's also the per-queue > MMIO control area too.
Ok. Always? Or just on powernv?
If it only has an MMIO presence on powernv, then the "core" xive
object should probably be TYPE_DEVICE, with the powernv specific
device being a SysBusDevice which incorporates the core xive device
inside it.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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