On 18/07/2017 12:55, James Hogan wrote: > The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 & > CP0_SegCtl2 control the behaviour and required privilege of the legacy > virtual memory segments. > > Add them to the CP0 interface so they can be read and written when > CP0_Config3.SC=1, and initialise them to describe the standard legacy > layout so they can be used in future patches regardless of whether they > are exposed to the guest. > > Signed-off-by: James Hogan <james.ho...@imgtec.com> > Cc: Yongbok Kim <yongbok....@imgtec.com> > Cc: Aurelien Jarno <aurel...@aurel32.net> > --- > Changes in v2: > - Use ld_tl and ext32s_tl rather than ld32s_tl to avoid big endian host, > MIPS64 target issues (Yongbok). > - Add missing break in DMFC0 CP0_SegCtl2 case. > --- > target/mips/cpu.h | 30 ++++++++++++++- > target/mips/helper.h | 3 +- > target/mips/machine.c | 7 ++- > target/mips/op_helper.c | 24 +++++++++++- > target/mips/translate.c | 88 ++++++++++++++++++++++++++++++++++++++++++- > 5 files changed, 150 insertions(+), 2 deletions(-) >
Reviewed-by: Yongbok Kim <yongbok....@imgtec.com> Regards, Yongbok