Signed-off-by: Lluís Vilanova <vilan...@ac.upc.edu>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Reviewed-by: Emilio G. Cota <c...@braap.org>
Tested-by: Emilio G. Cota <c...@braap.org>
---
target/i386/translate.c | 107 +++++++++--------------------------------------
1 file changed, 20 insertions(+), 87 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index a7c227203a..589b7da500 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -8449,6 +8449,11 @@ static void i386_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cpu)
cpu_cc_srcT = tcg_temp_local_new();
}
+static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu,
+ int *max_insns)
+{
+}
+
static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
@@ -8467,7 +8472,7 @@ static bool i386_tr_breakpoint_check(DisasContextBase
*dcbase, CPUState *cpu,
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
properly cleared -- thus we increment the PC here so that
- the logic setting tb->size below does the right thing. */
+ the generic logic setting tb->size later does the right thing. */
dc->base.pc_next += 1;
return true;
} else {
@@ -8538,94 +8543,22 @@ static void i386_tr_disas_log(const DisasContextBase
*dcbase,
}
-/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
-{
- DisasContext dc1, *dc = &dc1;
- int num_insns;
- int max_insns;
-
- /* generate intermediate code */
- dc->base.singlestep_enabled = cs->singlestep_enabled;
- dc->base.tb = tb;
- dc->base.is_jmp = DISAS_NEXT;
- dc->base.pc_first = tb->pc;
- dc->base.pc_next = dc->base.pc_first;
- i386_tr_init_disas_context(&dc->base, cs);
-
- num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
- }
-
- gen_tb_start(tb);
- for(;;) {
- i386_tr_insn_start(&dc->base, cs);
- num_insns++;
-
- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
- CPUBreakpoint *bp;
- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
- if (bp->pc == dc->base.pc_next) {
- if (i386_tr_breakpoint_check(&dc->base, cs, bp)) {
- break;
- }
- }
- }
-
- if (dc->base.is_jmp == DISAS_NORETURN) {
- break;
- }
- }
-
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
- }
-
- dc->base.pc_next = i386_tr_translate_insn(&dc->base, cs);
- /* stop translation if indicated */
- if (dc->base.is_jmp) {
- break;
- }
- /* if single step mode, we generate only one instruction and
- generate an exception */
- if (dc->base.singlestep_enabled) {
- dc->base.is_jmp = DISAS_TOO_MANY;
- break;
- }
- /* if too long translation, stop generation too */
- if (tcg_op_buf_full() ||
- num_insns >= max_insns) {
- dc->base.is_jmp = DISAS_TOO_MANY;
- break;
- }
- if (singlestep) {
- dc->base.is_jmp = DISAS_TOO_MANY;
- break;
- }
- }
- i386_tr_tb_stop(&dc->base, cs);
- if (tb->cflags & CF_LAST_IO)
- gen_io_end();
- gen_tb_end(tb, num_insns);
+static const TranslatorOps i386_tr_ops = {
+ .init_disas_context = i386_tr_init_disas_context,
+ .tb_start = i386_tr_tb_start,
+ .insn_start = i386_tr_insn_start,
+ .breakpoint_check = i386_tr_breakpoint_check,
+ .translate_insn = i386_tr_translate_insn,
+ .tb_stop = i386_tr_tb_stop,
+ .disas_log = i386_tr_disas_log,
+};
-#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(dc->base.pc_first)) {
- qemu_log_lock();
- qemu_log("----------------\n");
- i386_tr_disas_log(&dc->base, cs);
- qemu_log("\n");
- qemu_log_unlock();
- }
-#endif
+/* generate intermediate code for basic block 'tb'. */
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
+{
+ DisasContext dc;
- tb->size = dc->base.pc_next - dc->base.pc_first;
- tb->icount = num_insns;
+ translator_loop(&i386_tr_ops, &dc.base, cpu, tb);
}
void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,
