Hi Eric,
On 09.07.2017 22:51, Eric Auger wrote:
From: Prem Mallappa <prem.malla...@broadcom.com>
Introduces the SMMUv3 derived model. This is based on
System MMUv3 specification (v17).
Signed-off-by: Prem Mallappa <prem.malla...@broadcom.com>
Signed-off-by: Eric Auger <eric.au...@redhat.com>
---
v4 -> v5:
- change smmuv3_translate proto (IOMMUAccessFlags flag)
- has_stagex replaced by is_ste_stagex
- smmu_cfg_populate removed
- added smmuv3_decode_config and reworked error management
- remwork the naming of IOMMU mrs
- fix SMMU_CMDQ_CONS offset
[...]
+
+static void smmu_update_qreg(SMMUV3State *s, SMMUQueue *q, hwaddr reg,
+ uint32_t off, uint64_t val, unsigned size)
+{
+ if (size == 8 && off == 0) {
+ smmu_write64_reg(s, reg, val);
Based on my observation we never get here.
If I read the code correctly,
memory_region_dispatch_{write|read}()->memory_region_{write|read}_accessor()
will cut all 8-bytes accesses into 4-bytes slices. However, this makes
my SMMUv3 register handling happy:
static const MemoryRegionOps smmu_mem_ops = {
.read = smmu_read_mmio,
.write = smmu_write_mmio,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 8,
},
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+ },
};
Thanks,
Tomasz
