On 07/11/2017 03:27 PM, David Gibson wrote:
> On Tue, Jul 11, 2017 at 11:01:15AM +0200, Cédric Le Goater wrote:
>> On 07/10/2017 11:00 PM, Benjamin Herrenschmidt wrote:
>>> On Mon, 2017-07-10 at 14:49 +0200, Cédric Le Goater wrote:
>>>> On 07/10/2017 12:26 PM, David Gibson wrote:
>>>>> On Wed, Jul 05, 2017 at 07:13:16PM +0200, Cédric Le Goater wrote:
>>>>>> Prepare ground for the new exception model XIVE of POWER9.
>>>>>
>>>>> I'm a bit confused by this. The excp_model is about the CPU core's
>>>>> irq model, not the external irq controller's.
>>>>
>>>> yes this is true, but the POWER9 CPU is the only criteria we have
>>>> to distinguish a machine supporting XIVE and XICS from one only
>>>> supporting XICS.
>>>
>>> Why ? I don't understand.
>>>
>>> We do want an EXCP_POWER9 for other things, like the fact that we have
>>> a separate interrupt input for hypervisor, with associated vectors
>>> etc... but that still doesn't relate to what interrupt controller is
>>> there.
>>>
>>>> My idea was to use this flag to activate the OV5_XIVE_EXPLOIT bit
>>>> in ibm,arch-vec-5-platform-support ov5_platform, like this is done
>>>> for the MMU. See spapr_dt_ov5_platform_support()
>>>
>>> I disagree, the MMU is in the core, the XIVE isn't. It would be
>>> possibly to make a P9 core if a XICS in theory :-)
>>
>> ok. I understand. We could even "build" one in QEMU. HW would be
>> another story ...
>>
>> So should XIVE support be a sPAPR machine property only enabled if
>> 'cpu_model' matches "POWER9.*" ? The XICS/XIVE initialization is done
>> quite early in the machine init so this needs some checks.
>
> Basically, yes. The interrupt controller setup is generally something
> the machine looks after. What I'd actually suggest is a machine
> parameter for XICS vs. XIVE, whose default value is based on the CPU
> model.
yes. That is what I have been starting to work with now :
+static bool ppc_support_xive(MachineState *machine)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(first_cpu);
+
+ return pcc->pvr_match(pcc, CPU_POWERPC_POWER9_BASE);
+}
I am using the PVR to catch the cpu 'host' model. We could add
later on a machine property to disable the XIVE mode.
> Just as we could build a POWER9 with XICS in qemu, we could build a
> POWER8 with XIVE.
That might be the case with a POWER9 running in POWER8 compat mode.
I need to check.
Thanks,
C.
>>>>> Now.. I could imagine the POWER9 having a different core model that
>>>>> came along with XIVE, but I can't see this new model being used for
>>>>> anything anywhere in the rest of the series.
>>>>
>>>> See patch 26. But, maybe, I am taking a shortcut and we need another
>>>> family of flags.
>>>
>>> Or just some kind of enum for the interrupt controller, how do we do
>>> with OpenPIC vs. XICS already ? Old POWER3 had OpenPIC.
>>
>> AFAICT, we don't have such a CPU in QEMU/ppc.
>
> More to the point we don't have any machine type for those old POWER3
> setups.
>
>> We could use some extra flag to change the ICS behavior. The path I am
>> taking duplicates the ICS code but in real, we only need to change the
>> irq handlers.
>>
>> Thanks,
>>
>> C.
>>
>
