The POWER9 processor introduces a new operating mode of the decrementer called large decrementer mode.
If large decrementer mode is disabled then the decrementer behaves before as a 32-bit decrementing register. If large decrementer mode is enabled then the decrementer behaves as a d-bit decrementing register, the value of which is sign extended to 64-bits (where d is implementation dependent). The hypervisor decrementer is now a h-bit decrementing register which is always sign extended to 64-bits (where h is implementation dependent). To use the large decrementer both the guest and the host must have support for it. If the host has support then qemu will advertise this to the guest and tell the host that the guest is using the large decrementer. In TCG we always advertise support and enable the large decrementer if we detect that the guest will use it. The large decrementer can be disabled on the command line to ensure migration between hosts with differing levels of support or decrementer size. This patch series is based on the branch dwg/ppc-for-2.10 Suraj Jitindar Singh (5): target/ppc: Implement large decrementer support for TCG target/ppc: Implement large decrementer support for KVM target/ppc: Implement migration support for large decrementer target/ppc: Enable the large decrementer for TCG and KVM guests target/ppc: Add cmd line option to disable the large decrementer hw/ppc/ppc.c | 81 +++++++++++++++++++--------- hw/ppc/spapr.c | 128 ++++++++++++++++++++++++++++++++++++++++++++ hw/ppc/spapr_hcall.c | 36 +++++++++++++ include/hw/ppc/spapr.h | 2 + target/ppc/cpu-qom.h | 1 + target/ppc/cpu.h | 8 +-- target/ppc/kvm.c | 59 ++++++++++++++++++++ target/ppc/kvm_ppc.h | 25 +++++++++ target/ppc/mmu-hash64.c | 2 +- target/ppc/translate.c | 2 +- target/ppc/translate_init.c | 3 ++ 11 files changed, 317 insertions(+), 30 deletions(-) -- 2.9.4
