28.04.2017 15:56, Luc MICHEL wrote: > This patch adds the cp15, CRn=15, opc1=0, CRm=5, opc2=0 coprocessor > instruction > to the cortex-r5. As stated in the TRM, this instruction invalidates all the > data cache. This trivial patch implements it as NOP as cache operations are > not > implemented in QEMU. > > The documentation is here: > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460d/Bgbdbdjc.html
Applied to -trivial, since no one else picked it up so far :) Thanks, /mjt
