Because the code in PMON and Linux kernel use these bits to verify r/w operations. If one of them is 1 after r/w, PMON and Linux will consider r/w has failed. I guess that software will not set them to 1, because it is set by hardware when operation fails.
On Thu, Oct 28, 2010 at 12:12 AM, Michael S. Tsirkin <m...@redhat.com> wrote: > I see code in bonito.c that clears bits: > PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT > on each read and write. > > However > 1. I don't see anything in code that would set these bits > 2. The PCI spec says this about the status register: > > Reads to this register behave normally. Writes are slightly different > in > that bits can be reset, but not set. A one bit is reset (if it is not > read-only) whenever the register is written, and the write data in the > corresponding bit location is a 1. For instance, to clear bit 14 and > not > affect any other bits, write the value 0100_0000_0000_0000b to the > register. > > while the code in bonito.c resets the bits to 0 on each write. > > Comments? > > -- > MST > -- Huacai Chen
