Hi, This patch series improves the exception vectoring on the OpenRISC platform by adding support for both the EVBAR register and EPH bit.
This is my first patch to upstream QEMU, so please do point of if I have done anything silly. Tim 'mithro' Ansell (2): target/openrisc: Implement EVBAR register target/openrisc: Implement EPH bit target/openrisc/cpu.c | 2 ++ target/openrisc/cpu.h | 7 +++++++ target/openrisc/interrupt.c | 9 ++++++++- target/openrisc/sys_helper.c | 7 +++++++ 4 files changed, 24 insertions(+), 1 deletion(-) -- 2.12.1
