On 24 March 2017 at 06:14, Wangjintang <wangjint...@huawei.com> wrote:
> Hi Pranith,
>
> Thanks for your reply. patch as below, new added code default is off,
> please review.
> The major thinking is about translate Armv8's prefetch instruction into
> intermediate code, at the same time don't effect the rm/rn register.
>
>
> diff --git a/translate-a64.c b/translate-a64.c
> index 814f30f..86da8ee 100644
> --- a/translate-a64.c
> +++ b/translate-a64.c
> @@ -2061,7 +2061,11 @@ static void disas_ld_lit(DisasContext *s, uint32_t
> insn)
> } else {
> if (opc == 3) {
> /* PRFM (literal) : prefetch */
> + #ifdef TCG_AARCH64_PREFETCH_TRANSLATE
> + ;
> + #else
> return;
> + #endif
> }
No, these changes look wrong. PRFM instructions do not need to
do anything and should definitely not be emitting any intermediate
code. In particular if you let execution fall through and try
do_gpr_ld() then it will really do a load, which might cause
an exception -- this is specifically forbidden for PRFM.
Architecturally the ARM ARM says "it is valid for the PE to
treat any or all prefetch instructions as a NOP", which is
what QEMU does.
The existing code is correct. In general you should not
expect to be able to deduce the guest instructions from
the intermediate code representation.
thanks
-- PMM
