Peter Maydell <peter.mayd...@linaro.org> writes:
> On 16 February 2017 at 16:35, Peter Maydell <peter.mayd...@linaro.org> wrote:
>> From: Michael Davidsaver <mdavidsa...@gmail.com>
>>
>> Despite some superficial similarities of register layout, the
>> M-profile NVIC is really very different from the A-profile GIC.
>> Our current attempt to reuse the GIC code means that we have
>> significant bugs in our NVIC.
>>
>> Implement the NVIC as an entirely separate device, to give
>> us somewhere we can get the behaviour correct.
>>
>> This initial commit does not attempt to implement exception
>> priority escalation, since the GIC-based code didn't either.
>> It does fix a few bugs in passing:
>> * ICSR.RETTOBASE polarity was wrong and didn't account for
>> internal exceptions
>> * ICSR.VECTPENDING was 16 too high if the pending exception
>> was for an external interrupt
>> * UsageFault, BusFault and MemFault were not disabled on reset
>> as they are supposed to be
>>
>> Signed-off-by: Michael Davidsaver <mdavidsa...@gmail.com>
>> [PMM: reworked, various bugs and stylistic cleanups]
>> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
>
>> + case 0x400 ... 0x5ef: /* NVIC Priority */
>> + startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
>> +
>> + for (i = 0; i < size; i++) {
>
> Just noticed this line should be
> + for (i = 0; i < size && startvec + i < s->num_irq; i++) {
>
> which brings it into line with the nvic_sysreg_read() code
> and prevents an assert() in set_prio() if the guest writes to
> registers beyond the end of the implemented IRQ range.
>
>> + set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);
>> + }
>> + nvic_irq_update(s);
>> + return;
>
> Unless there's some other problem that means I need
> to respin anyway I propose to just squash in that fix.
With the squashed fix:
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
>
> thanks
> -- PMM
--
Alex Bennée
