On 02/09/2017 05:07 PM, Bystricky, Juro wrote:
>>>> [...]
>>>>
>>>>>>> +static uint64_t altera_juart_read(void *opaque, hwaddr addr,
>> unsigned
>>>>>> int size)
>>>>>>> +{
>>>>>>> + AlteraJUARTState *s = opaque;
>>>>>>> + uint32_t r;
>>>>>>> +
>>>>>>> + addr >>= 2;
>>>>>>
>>>>>> Hmmmmm, how will unaligned read from one of these registers be handled
>>>>>> on real HW ? ie. read from address 0x3 ? What about writes ?
>>>>>>
>>>>>
>>>>> there is no reading/writing going on via "addr".
>>>>> This just maps the hw address into register number, where registers are
>>>> at
>>>>> 4 bytes boundaries (so they are aligned as needed) but indexed as
>>>> 1,2,3....
>>>>> (Pretty common code in other drivers.)
>>>>> But will redo the code anyway so there are no shifts.
>>>>
>>>> This doesn't answer my question at all. How does real hardware behave if
>>>> you read from unaligned address in the register space , ie. offset 0x3 ?
>>>>
>>>
>>> Not sure I understand the question here. Which "real hardware" are we
>> talking about?
>>
>> By real hardware I mean real Nios2 system ...
>>
>>> If "real hardware" contains MMU or MPU then an exception is generated on
>> misalign access.
>>
>> Is this handled here or not ?
>>
>
> Sorry, I am not sure I understand the question.
> Exceptions are handled by interrupt controller.
> This code for JTAG UART does not have any misaligned accesses.
>
>
The code running on nios2 can issue unaligned access to the jtag uart
registers, yes ? If that happens, what happens on real HW and how is
this emulated ?
--
Best regards,
Marek Vasut
