I CC: Xilinx Zynq Maintainers.
Laurent
On 07/12/2016 22:12, Andrew Gacek wrote:
> When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to
> 0, the receiver timeout counter should be disabled. See page 1801 of
> "Zynq-7000 AP SoC Technical Reference Manual". This commit adds a
> such a check before setting the receive timeout interrupt.
>
> Signed-off-by: Andrew Gacek <andrew.ga...@gmail.com>
> ---
> hw/char/cadence_uart.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> index 0215d65..54194b1 100644
> --- a/hw/char/cadence_uart.c
> +++ b/hw/char/cadence_uart.c
> @@ -138,7 +138,9 @@ static void fifo_trigger_update(void *opaque)
> {
> CadenceUARTState *s = opaque;
>
> - s->r[R_CISR] |= UART_INTR_TIMEOUT;
> + if (s->r[R_RTOR]) {
> + s->r[R_CISR] |= UART_INTR_TIMEOUT;
> + }
>
> uart_update_status(s);
> }
>
