On 2016年12月08日 10:16, Peter Xu wrote:
On Thu, Dec 08, 2016 at 10:02:15AM +0800, Jason Wang wrote:
On 2016年12月07日 13:52, Peter Xu wrote:
Currently vt-d Context Entry (CE) only allows 39/48 bits address width.
If guest software configured more than that, we complain and force
shrink to the maximum supported, which is 48bits.
Signed-off-by: Peter Xu <pet...@redhat.com>
---
hw/i386/intel_iommu.c | 12 +++++++++++-
hw/i386/intel_iommu_internal.h | 2 ++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 5f3e351..98d45ef 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -601,7 +601,17 @@ static inline uint32_t
vtd_get_level_from_context_entry(VTDContextEntry *ce)
static inline uint32_t vtd_get_agaw_from_context_entry(VTDContextEntry *ce)
{
- return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
+ uint8_t aw = (ce->hi & VTD_CONTEXT_ENTRY_AW);
+ /*
+ * According to vt-d spec 10.4.2 bits 12:8, SAGAW only allows
+ * 39/48 bits.
+ */
+ if (aw > VTD_CE_AW_48BIT) {
+ error_report("Context entry address width not supported (aw=%d), "
+ "Shrinking to maximum.", aw);
+ aw = VTD_CE_AW_48BIT;
+ }
Is this behavior specified by spec?
That's how I understand spec 10.4.2 bits 12:8 (as mentioned in above
comment). Only 39/48 bits AGAW are allowed, and others are reserved.
When writting up this patch, I thought illegal value for this aw bits
(from guest software) might cause trouble, but I was wrong, since we
have a "MIN(ce_agaw, VTD_MGAW)" check later on. So that won't be a
problem, and this patch is not that necessary now.
Thanks,
-- peterx
Yes, and it can even report DMAR fault to guest which is better.
Thanks
