From: Prasad J Pandit <p...@fedoraproject.org> The Cadence UART device emulator calculates speed by dividing the baud rate by a 'baud rate generator' & 'baud rate divider' value. The device specification defines these register values to be non-zero and within certain limits. Add checks for these limits to avoid errors like divide by zero.
Reported-by: Huawei PSIRT <ps...@huawei.com> Signed-off-by: Prasad J Pandit <p...@fedoraproject.org> Reviewed-by: Alistair Francis <alistair.fran...@xilinx.com> Message-id: 1477596278-1470-1-git-send-email-ppan...@redhat.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> --- hw/char/cadence_uart.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index def34cd..0215d65 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -1,6 +1,11 @@ /* * Device model for Cadence UART * + * Reference: Xilinx Zynq 7000 reference manual + * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf + * - Chapter 19 UART Controller + * - Appendix B for Register details + * * Copyright (c) 2010 Xilinx Inc. * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwa...@petalogix.com) * Copyright (c) 2012 PetaLogix Pty Ltd. @@ -402,6 +407,16 @@ static void uart_write(void *opaque, hwaddr offset, break; } break; + case R_BRGR: /* Baud rate generator */ + if (value >= 0x01) { + s->r[offset] = value & 0xFFFF; + } + break; + case R_BDIV: /* Baud rate divider */ + if (value >= 0x04) { + s->r[offset] = value & 0xFF; + } + break; default: s->r[offset] = value; } -- 2.7.4
