On 31/10/2016 18:20, Eduardo Habkost wrote: > On Mon, Oct 31, 2016 at 04:27:26PM +0800, He Chen wrote: >> From: Luwei Kang <luwei.k...@intel.com> >> >> The spec can be found in Intel Software Developer Manual or in >> Instruction Set Extensions Programming Reference. >> >> Signed-off-by: Luwei Kang <luwei.k...@intel.com> >> Signed-off-by: Piotr Luc <piotr....@intel.com> >> >> --- >> Changes in v2: >> * correct TCG_7_0_EDX_FEATURES. > > Reviewed-by: Eduardo Habkost <ehabk...@redhat.com> > > Applied to x86-next with the following fixup:
I have already sent a pull request for this patch, sorry. Paolo > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index c605724..6c6f8ae 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -631,7 +631,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_7_0_ECX_RDPID (1U << 22) > > #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network > Instructions */ > -#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply > Accumulation Single Precision */ > +#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation > + * Single Precision */ > > #define CPUID_XSAVE_XSAVEOPT (1U << 0) > #define CPUID_XSAVE_XSAVEC (1U << 1) >
