On 12/10/2016 06:44, David Gibson wrote: > Currently the functions in pci-spapr.c (like pci-pc.c on which it's based) > don't distinguish between 32-bit and 64-bit PCI MMIO. At the moment, the > qemu side implementation is a bit weird and has a single MMIO window > straddling 32-bit and 64-bit regions, but we're likely to change that in > future. > > In any case, pci-pc.c - and therefore the testcases using PCI - only handle > 32-bit MMIOs for now. For spapr despite whatever changes might happen with > the MMIO windows, the 32-bit window is likely to remain at 2..4 GiB in PCI > space. > > So, explicitly limit pci-spapr.c to 32-bit MMIOs for now, we can add 64-bit > MMIO support back in when and if we need it. > > Signed-off-by: David Gibson <da...@gibson.dropbear.id.au>
Reviewed-by: Laurent Vivier <lviv...@redhat.com> > --- > tests/libqos/pci-spapr.c | 32 +++++++++++++++----------------- > 1 file changed, 15 insertions(+), 17 deletions(-) > > diff --git a/tests/libqos/pci-spapr.c b/tests/libqos/pci-spapr.c > index 3192903..558dfc3 100644 > --- a/tests/libqos/pci-spapr.c > +++ b/tests/libqos/pci-spapr.c > @@ -32,8 +32,8 @@ typedef struct QPCIBusSPAPR { > uint64_t pio_cpu_base; > QPCIWindow pio; > > - uint64_t mmio_cpu_base; > - QPCIWindow mmio; > + uint64_t mmio32_cpu_base; > + QPCIWindow mmio32; > > uint64_t pci_hole_start; > uint64_t pci_hole_size; > @@ -58,7 +58,7 @@ static uint8_t qpci_spapr_io_readb(QPCIBus *bus, void *addr) > if (port < s->pio.size) { > v = readb(s->pio_cpu_base + port); > } else { > - v = readb(s->mmio_cpu_base + port); > + v = readb(s->mmio32_cpu_base + port); > } > return v; > } > @@ -71,7 +71,7 @@ static uint16_t qpci_spapr_io_readw(QPCIBus *bus, void > *addr) > if (port < s->pio.size) { > v = readw(s->pio_cpu_base + port); > } else { > - v = readw(s->mmio_cpu_base + port); > + v = readw(s->mmio32_cpu_base + port); > } > return bswap16(v); > } > @@ -84,7 +84,7 @@ static uint32_t qpci_spapr_io_readl(QPCIBus *bus, void > *addr) > if (port < s->pio.size) { > v = readl(s->pio_cpu_base + port); > } else { > - v = readl(s->mmio_cpu_base + port); > + v = readl(s->mmio32_cpu_base + port); > } > return bswap32(v); > } > @@ -96,7 +96,7 @@ static void qpci_spapr_io_writeb(QPCIBus *bus, void *addr, > uint8_t value) > if (port < s->pio.size) { > writeb(s->pio_cpu_base + port, value); > } else { > - writeb(s->mmio_cpu_base + port, value); > + writeb(s->mmio32_cpu_base + port, value); > } > } > > @@ -108,7 +108,7 @@ static void qpci_spapr_io_writew(QPCIBus *bus, void > *addr, uint16_t value) > if (port < s->pio.size) { > writew(s->pio_cpu_base + port, value); > } else { > - writew(s->mmio_cpu_base + port, value); > + writew(s->mmio32_cpu_base + port, value); > } > } > > @@ -120,7 +120,7 @@ static void qpci_spapr_io_writel(QPCIBus *bus, void > *addr, uint32_t value) > if (port < s->pio.size) { > writel(s->pio_cpu_base + port, value); > } else { > - writel(s->mmio_cpu_base + port, value); > + writel(s->mmio32_cpu_base + port, value); > } > } > > @@ -235,12 +235,9 @@ static void qpci_spapr_iounmap(QPCIBus *bus, void *data) > /* FIXME */ > } > > -#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL > #define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL > -#define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL > -#define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000 > -#define SPAPR_PCI_MMIO_WIN_SIZE (SPAPR_PCI_WINDOW_SPACING - \ > - SPAPR_PCI_MEM_WIN_BUS_OFFSET) > +#define SPAPR_PCI_MMIO32_WIN_OFF 0xA0000000 > +#define SPAPR_PCI_MMIO32_WIN_SIZE 0x80000000 /* 2 GiB */ > #define SPAPR_PCI_IO_WIN_OFF 0x80000000 > #define SPAPR_PCI_IO_WIN_SIZE 0x10000 > > @@ -280,13 +277,14 @@ QPCIBus *qpci_init_spapr(QGuestAllocator *alloc) > ret->pio.pci_base = 0; > ret->pio.size = SPAPR_PCI_IO_WIN_SIZE; > > - ret->mmio_cpu_base = SPAPR_PCI_WINDOW_BASE + SPAPR_PCI_MMIO_WIN_OFF; > - ret->mmio.pci_base = SPAPR_PCI_MEM_WIN_BUS_OFFSET; > - ret->mmio.size = SPAPR_PCI_MMIO_WIN_SIZE; > + /* 32-bit portion of the MMIO window is at PCI address 2..4 GiB */ > + ret->mmio32_cpu_base = SPAPR_PCI_WINDOW_BASE + SPAPR_PCI_MMIO32_WIN_OFF; > + ret->mmio32.pci_base = 0x80000000; /* 2 GiB */ > + ret->mmio32.size = SPAPR_PCI_MMIO32_WIN_SIZE; > > ret->pci_hole_start = 0xC0000000; > ret->pci_hole_size = > - ret->mmio.pci_base + ret->mmio.size - ret->pci_hole_start; > + ret->mmio32.pci_base + ret->mmio32.size - ret->pci_hole_start; > ret->pci_hole_alloc = 0; > > ret->pci_iohole_start = 0xc000; >