On 10/10/2016 04:45 PM, Artyom Tarasenko wrote:
Hmm. Would it make more sense to reorg these as
TTE_US1_*
TTE_UA2005_*
with some duplication for the bits that are shared?
As is, it's pretty hard to tell which actually change...
All of them :-)
I'm not sure about renaming: the US1 format is still used in T1 on the read
access.
On the other hand, it's not used in T2. And then again we don't have the T2
emulation yet.
Oh my. Different on T2 as well?
I wonder if it would make sense to have different functions with which to fill
in the CPUClass hooks (or invent new SPARCCPUClass hooks as necessary) for the
major entry points.
E.g. sparc_cpu_handle_mmu_fault or get_physical_address could be hooked, so
that the choice of how to handle the tlb miss is chosen at startup time, and
not during each fault. One can arrange subroutines as necessary to share code
between the alternate routines, such as when T1 needs to use parts of US1.
Similarly for out-of-line ASI handling, which is already beyond messy, with
handling for all cpus thrown in the same switch statement.
r~
