David Gibson <da...@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Wed, Sep 28, 2016 at 11:01:20AM +0530, Nikunj A Dadhania wrote:
>> From: Ravi Bangoria <ravi.bango...@linux.vnet.ibm.com>
>>
>> mtvsrdd: Move To VSR Double Doubleword
>>
>> Signed-off-by: Ravi Bangoria <ravi.bango...@linux.vnet.ibm.com>
>> Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com>
>> ---
>> target-ppc/translate/vsx-impl.inc.c | 23 +++++++++++++++++++++++
>> target-ppc/translate/vsx-ops.inc.c | 1 +
>> 2 files changed, 24 insertions(+)
>>
>> diff --git a/target-ppc/translate/vsx-impl.inc.c
>> b/target-ppc/translate/vsx-impl.inc.c
>> index b669e8c..f9db1d4 100644
>> --- a/target-ppc/translate/vsx-impl.inc.c
>> +++ b/target-ppc/translate/vsx-impl.inc.c
>> @@ -234,6 +234,29 @@ static void gen_mfvsrld(DisasContext *ctx)
>> tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_vsrl(xS(ctx->opcode)));
>> }
>>
>> +static void gen_mtvsrdd(DisasContext *ctx)
>> +{
>> + if (xT(ctx->opcode) < 32) {
>> + if (unlikely(!ctx->vsx_enabled)) {
>> + gen_exception(ctx, POWERPC_EXCP_VSXU);
>> + return;
>> + }
>> + } else {
>> + if (unlikely(!ctx->altivec_enabled)) {
>> + gen_exception(ctx, POWERPC_EXCP_VPU);
>> + return;
>> + }
>> + }
>
> Huh.. so in the ISA doc version I have at least (p114), the
> pseudo-code for the instruction states either vector or VSX
> exceptions. The text however says either FP or vector exceptions.
>
> The pseudo-code version seems more sensible which is what you've
> implemented, so I'm guessing this is just an error in the descriptive
> text.
Right.
> It'd be nice to confirm that against real hardware behaviour if
> possible though.
Sure, will check it.
Regards,
Nikunj
