On Tue, 2016-09-06 at 07:25 +0530, Nikunj A Dadhania wrote: > > Benjamin Herrenschmidt <b...@kernel.crashing.org> writes: > > > > > On Sun, 2016-09-04 at 18:00 +0100, Alex Bennée wrote: > > > > > > > > When is the synchronisation point? On ARM we end the basic block on > > > system instructions that mess with the cache. As a result the flush > > > is done as soon as we exit the run loop on the next instruction. > > > > Talking o this... Nikunj, I notice, all our TLB flushing is only ever > > done on the "current" CPU. I mean today, without MT-TCG. That looks > > broken already isn't it ? > > Without MT-TCG, there was only one cpu, so I think we never hit that > issue.
No there isn't. You can start qemu with --smp 4 and have 4 CPUs. It will alternate between them, but they *will* have differrent TLBs.
