ARM1176 CPUs support the Vector Base Address Register but currently,
qemu only supports VBAR on ARMv7 CPUs. Fix this by adding a new
feature ARM_FEATURE_VBAR which is used for ARMv7 and ARM1176 CPUs.
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
target-arm/cpu.c | 2 ++
target-arm/cpu.h | 1 +
target-arm/helper.c | 18 ++++++++++++------
3 files changed, 15 insertions(+), 6 deletions(-)
Index: qemu-aspeed.git/target-arm/helper.c
===================================================================
--- qemu-aspeed.git.orig/target-arm/helper.c
+++ qemu-aspeed.git/target-arm/helper.c
@@ -1251,12 +1251,6 @@ static const ARMCPRegInfo v7_cp_reginfo[
.access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
.writefn = pmintenclr_write },
- { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .writefn = vbar_write,
- .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
- offsetof(CPUARMState, cp15.vbar_ns) },
- .resetvalue = 0 },
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
@@ -1410,6 +1404,15 @@ static const ARMCPRegInfo v6k_cp_reginfo
.resetvalue = 0 },
REGINFO_SENTINEL
};
+static const ARMCPRegInfo vbar_cp_reginfo[] = {
+ { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL1_RW, .writefn = vbar_write,
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
+ offsetof(CPUARMState, cp15.vbar_ns) },
+ .resetvalue = 0 },
+ REGINFO_SENTINEL
+};
#ifndef CONFIG_USER_ONLY
@@ -4486,6 +4489,9 @@ void register_cp_regs_for_features(ARMCP
if (arm_feature(env, ARM_FEATURE_V6K)) {
define_arm_cp_regs(cpu, v6k_cp_reginfo);
}
+ if (arm_feature(env, ARM_FEATURE_VBAR)) {
+ define_arm_cp_regs(cpu, vbar_cp_reginfo);
+ }
if (arm_feature(env, ARM_FEATURE_V7MP) &&
!arm_feature(env, ARM_FEATURE_MPU)) {
define_arm_cp_regs(cpu, v7mp_cp_reginfo);
Index: qemu-aspeed.git/target-arm/cpu.h
===================================================================
--- qemu-aspeed.git.orig/target-arm/cpu.h
+++ qemu-aspeed.git/target-arm/cpu.h
@@ -1129,6 +1129,7 @@ enum arm_features {
ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
+ ARM_FEATURE_VBAR, /* has cp15 VBAR (ARM1176) */
};
static inline int arm_feature(CPUARMState *env, int feature)
Index: qemu-aspeed.git/target-arm/cpu.c
===================================================================
--- qemu-aspeed.git.orig/target-arm/cpu.c
+++ qemu-aspeed.git/target-arm/cpu.c
@@ -584,6 +584,7 @@ static void arm_cpu_realizefn(DeviceStat
set_feature(env, ARM_FEATURE_LPAE);
}
if (arm_feature(env, ARM_FEATURE_V7)) {
+ set_feature(env, ARM_FEATURE_VBAR);
set_feature(env, ARM_FEATURE_VAPA);
set_feature(env, ARM_FEATURE_THUMB2);
set_feature(env, ARM_FEATURE_MPIDR);
@@ -867,6 +868,7 @@ static void arm1176_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm1176";
set_feature(&cpu->env, ARM_FEATURE_V6K);
+ set_feature(&cpu->env, ARM_FEATURE_VBAR);
set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
