We don't implement imprecise FP exceptions and using store_current
which sets SRR1 to the *previous* instruction never makes sense
for these. So let's be truthful and make them precise, which is
allowed by the architecture.
Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org>
---
target-ppc/excp_helper.c | 11 ++++++-----
target-ppc/translate.c | 1 -
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 96c6fd9..02d9e79 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -274,12 +274,13 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
env->error_code = 0;
return;
}
+
+ /* FP exceptions always have NIP pointing to the faulting
+ * instruction, so always use store_next and claim we are
+ * precise in the MSR.
+ */
msr |= 0x00100000;
- if (msr_fe0 == msr_fe1) {
- goto store_next;
- }
- msr |= 0x00010000;
- break;
+ goto store_next;
case POWERPC_EXCP_INVAL:
LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
msr |= 0x00080000;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3cfa40f..ba14bda 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3060,7 +3060,6 @@ static void gen_conditional_store(DisasContext *ctx, TCGv
EA,
int reg, int size)
{
TCGv t0 = tcg_temp_new();
- uint32_t save_exception = ctx->exception;
tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
tcg_gen_movi_tl(t0, (size << 5) | reg);
--
2.7.4
