For devices, delete explicit PCI byte swaps. At big endian host bridges,
change MMIO registration to insert a byte swapping IO type.
Signed-off-by: Blue Swirl <blauwir...@gmail.com>
---
hw/apb_pci.c | 1 +
hw/e1000.c | 6 ------
hw/grackle_pci.c | 14 ++++++++++++++
hw/gt64xxx.c | 16 ++++++++++++++++
hw/ppc4xx_pci.c | 17 +++++++++++++++++
hw/ppce500_pci.c | 15 +++++++++++++++
hw/prep_pci.c | 14 ++++++++++++++
hw/rtl8139.c | 12 ------------
hw/sh_pci.c | 16 ++++++++++++++++
hw/unin_pci.c | 16 ++++++++++++++++
hw/usb-ohci.c | 7 -------
hw/versatile_pci.c | 15 +++++++++++++++
hw/vga-pci.c | 2 +-
13 files changed, 125 insertions(+), 26 deletions(-)
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index cbc11ab..295b673 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -320,6 +320,7 @@ static void apb_register_mem(void *opaque,
pcibus_t addr, pcibus_t size,
APB_DPRINTF("%s: addr %" FMT_PCIBUS " size %" FMT_PCIBUS " mm %x\n",
__func__, addr, size, mm);
+ mm = cpu_physical_memory_toggle_bswap(mm);
cpu_register_physical_memory(addr + d->mem_base, size, mm);
}
diff --git a/hw/e1000.c b/hw/e1000.c
index 200a69d..73c1de1 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -821,9 +821,6 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t
addr, uint32_t val)
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
if (index < NWRITEOPS && macreg_writeops[index])
macreg_writeops[index](s, index, val);
else if (index < NREADOPS && macreg_readops[index])
@@ -858,9 +855,6 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
if (index < NREADOPS && macreg_readops[index])
{
uint32_t val = macreg_readops[index](s, index);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
return val;
}
DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index b9d28a1..ad70ef2 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -78,6 +78,18 @@ static void pci_grackle_reset(void *opaque)
{
}
+static void grackle_register_mem(void *opaque, pcibus_t addr, pcibus_t size,
+ int mm)
+{
+ mm = cpu_physical_memory_toggle_bswap(mm);
+ cpu_register_physical_memory(addr, size, mm);
+}
+
+static void grackle_unregister_mem(void *opaque, pcibus_t addr, pcibus_t size)
+{
+ cpu_register_physical_memory(addr, size, IO_MEM_UNASSIGNED);
+}
+
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
{
DeviceState *dev;
@@ -92,6 +104,8 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
pci_grackle_set_irq,
pci_grackle_map_irq,
pic, 0, 4);
+ pci_bus_set_register_mem_fn(d->host_state.bus, grackle_register_mem,
+ grackle_unregister_mem, d);
pci_create_simple(d->host_state.bus, 0, "grackle");
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index cabf7ea..477ce69 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -1105,6 +1105,20 @@ static int gt64120_load(QEMUFile* f, void
*opaque, int version_id)
return 0;
}
+static void gt64120_register_mem(void *opaque, pcibus_t addr, pcibus_t size,
+ int mm)
+{
+#ifdef TARGET_WORDS_BIGENDIAN
+ mm = cpu_physical_memory_toggle_bswap(mm);
+#endif
+ cpu_register_physical_memory(addr, size, mm);
+}
+
+static void gt64120_unregister_mem(void *opaque, pcibus_t addr, pcibus_t size)
+{
+ cpu_register_physical_memory(addr, size, IO_MEM_UNASSIGNED);
+}
+
PCIBus *pci_gt64120_init(qemu_irq *pic)
{
GT64120State *s;
@@ -1116,6 +1130,8 @@ PCIBus *pci_gt64120_init(qemu_irq *pic)
s->pci->bus = pci_register_bus(NULL, "pci",
pci_gt64120_set_irq, pci_gt64120_map_irq,
pic, PCI_DEVFN(18, 0), 4);
+ pci_bus_set_register_mem_fn(s->pci->bus, gt64120_register_mem,
+ gt64120_unregister_mem, s);
s->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, s);
d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
0, NULL, NULL);
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index 7a7b251..a4405f4 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -331,6 +331,20 @@ static int ppc4xx_pci_load(QEMUFile *f, void
*opaque, int version_id)
return 0;
}
+static void ppc4xx_register_mem(void *opaque, pcibus_t addr, pcibus_t size,
+ int mm)
+{
+#ifdef TARGET_WORDS_BIGENDIAN
+ mm = cpu_physical_memory_toggle_bswap(mm);
+#endif
+ cpu_register_physical_memory(addr, size, mm);
+}
+
+static void ppc4xx_unregister_mem(void *opaque, pcibus_t addr, pcibus_t size)
+{
+ cpu_register_physical_memory(addr, size, IO_MEM_UNASSIGNED);
+}
+
/* XXX Interrupt acknowledge cycles not supported. */
PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
target_phys_addr_t config_space,
@@ -349,6 +363,9 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
ppc4xx_pci_set_irq,
ppc4xx_pci_map_irq,
pci_irqs, 0, 4);
+ pci_bus_set_register_mem_fn(controller->pci_state.bus,
+ ppc4xx_register_mem,
+ ppc4xx_unregister_mem, controller);
controller->pci_dev = pci_register_device(controller->pci_state.bus,
"host bridge", sizeof(PCIDevice),
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index b5b7d25..e4288bd 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -267,6 +267,18 @@ static int ppce500_pci_load(QEMUFile *f, void
*opaque, int version_id)
return 0;
}
+static void ppce500_register_mem(void *opaque, pcibus_t addr, pcibus_t size,
+ int mm)
+{
+ mm = cpu_physical_memory_toggle_bswap(mm);
+ cpu_register_physical_memory(addr, size, mm);
+}
+
+static void ppce500_unregister_mem(void *opaque, pcibus_t addr, pcibus_t size)
+{
+ cpu_register_physical_memory(addr, size, IO_MEM_UNASSIGNED);
+}
+
PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
{
PPCE500PCIState *controller;
@@ -281,6 +293,9 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4],
target_phys_addr_t registers)
mpc85xx_pci_map_irq,
pci_irqs, PCI_DEVFN(0x11, 0),
4);
+ pci_bus_set_register_mem_fn(controller->pci_state.bus,
+ ppce500_register_mem,
+ ppce500_unregister_mem, controller);
d = pci_register_device(controller->pci_state.bus,
"host bridge", sizeof(PCIDevice),
0, NULL, NULL);
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index 16c677c..8867ee7 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -106,6 +106,18 @@ static void prep_set_irq(void *opaque, int
irq_num, int level)
qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level);
}
+static void prep_register_mem(void *opaque, pcibus_t addr, pcibus_t size,
+ int mm)
+{
+ mm = cpu_physical_memory_toggle_bswap(mm);
+ cpu_register_physical_memory(addr, size, mm);
+}
+
+static void prep_unregister_mem(void *opaque, pcibus_t addr, pcibus_t size)
+{
+ cpu_register_physical_memory(addr, size, IO_MEM_UNASSIGNED);
+}
+
PCIBus *pci_prep_init(qemu_irq *pic)
{
PREPPCIState *s;
@@ -116,6 +128,8 @@ PCIBus *pci_prep_init(qemu_irq *pic)
s->bus = pci_register_bus(NULL, "pci",
prep_set_irq, prep_map_irq, pic, 0, 4);
+ pci_bus_set_register_mem_fn(s->bus, prep_register_mem,
+ prep_unregister_mem, s);
pci_host_conf_register_ioport(0xcf8, s);
pci_host_data_register_ioport(0xcfc, s);
diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index bc20549..0deccf3 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -3125,17 +3125,11 @@ static void rtl8139_mmio_writeb(void *opaque,
target_phys_addr_t addr, uint32_t
static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t
addr, uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap16(val);
-#endif
rtl8139_io_writew(opaque, addr & 0xFF, val);
}
static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t
addr, uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
rtl8139_io_writel(opaque, addr & 0xFF, val);
}
@@ -3147,18 +3141,12 @@ static uint32_t rtl8139_mmio_readb(void
*opaque, target_phys_addr_t addr)
static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap16(val);
-#endif
return val;
}
static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
return val;
}
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index cc2f190..e968cbe 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -91,6 +91,20 @@ static MemOp sh_pci_reg = {
{ NULL, NULL, sh_pci_reg_write },
};
+static void sh_pci_register_mem(void *opaque, pcibus_t addr, pcibus_t size,
+ int mm)
+{
+#ifdef TARGET_WORDS_BIGENDIAN
+ mm = cpu_physical_memory_toggle_bswap(mm);
+#endif
+ cpu_register_physical_memory(addr, size, mm);
+}
+
+static void sh_pci_unregister_mem(void *opaque, pcibus_t addr, pcibus_t size)
+{
+ cpu_register_physical_memory(addr, size, IO_MEM_UNASSIGNED);
+}
+
PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *opaque, int devfn_min, int nirq)
{
@@ -101,6 +115,8 @@ PCIBus *sh_pci_register_bus(pci_set_irq_fn
set_irq, pci_map_irq_fn map_irq,
p->bus = pci_register_bus(NULL, "pci",
set_irq, map_irq, opaque, devfn_min, nirq);
+ pci_bus_set_register_mem_fn(p->bus, sh_pci_register_mem,
+ sh_pci_unregister_mem, p);
p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
-1, NULL, NULL);
reg = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, p);
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index 5517f69..99a12af 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -141,6 +141,18 @@ static uint32_t unin_data_read(ReadWriteHandler *handler,
return val;
}
+static void unin_register_mem(void *opaque, pcibus_t addr, pcibus_t size,
+ int mm)
+{
+ mm = cpu_physical_memory_toggle_bswap(mm);
+ cpu_register_physical_memory(addr, size, mm);
+}
+
+static void unin_unregister_mem(void *opaque, pcibus_t addr, pcibus_t size)
+{
+ cpu_register_physical_memory(addr, size, IO_MEM_UNASSIGNED);
+}
+
static int pci_unin_main_init_device(SysBusDevice *dev)
{
UNINState *s;
@@ -238,6 +250,8 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
pci_unin_set_irq, pci_unin_map_irq,
pic, PCI_DEVFN(11, 0), 4);
+ pci_bus_set_register_mem_fn(d->host_state.bus, unin_register_mem,
+ unin_unregister_mem, s);
#if 0
pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
#endif
@@ -289,6 +303,8 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic)
d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
pci_unin_set_irq, pci_unin_map_irq,
pic, PCI_DEVFN(11, 0), 4);
+ pci_bus_set_register_mem_fn(d->host_state.bus, unin_register_mem,
+ unin_unregister_mem, s);
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c
index 992400e..94f27cd 100644
--- a/hw/usb-ohci.c
+++ b/hw/usb-ohci.c
@@ -1530,9 +1530,6 @@ static uint32_t ohci_mem_read(void *ptr,
target_phys_addr_t addr)
}
}
-#ifdef TARGET_WORDS_BIGENDIAN
- retval = bswap32(retval);
-#endif
return retval;
}
@@ -1542,10 +1539,6 @@ static void ohci_mem_write(void *ptr,
target_phys_addr_t addr, uint32_t val)
addr &= 0xff;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
-
/* Only aligned reads are allowed on OHCI */
if (addr & 3) {
fprintf(stderr, "usb-ohci: Mis-aligned write\n");
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index a76bdfa..ad5c820 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -116,6 +116,20 @@ static void pci_vpb_map(SysBusDevice *dev,
target_phys_addr_t base)
}
}
+static void vpb_register_mem(void *opaque, pcibus_t addr, pcibus_t size,
+ int mm)
+{
+#ifdef TARGET_WORDS_BIGENDIAN
+ mm = cpu_physical_memory_toggle_bswap(mm);
+#endif
+ cpu_register_physical_memory(addr, size, mm);
+}
+
+static void vpb_unregister_mem(void *opaque, pcibus_t addr, pcibus_t size)
+{
+ cpu_register_physical_memory(addr, size, IO_MEM_UNASSIGNED);
+}
+
static int pci_vpb_init(SysBusDevice *dev)
{
PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
@@ -128,6 +142,7 @@ static int pci_vpb_init(SysBusDevice *dev)
bus = pci_register_bus(&dev->qdev, "pci",
pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
PCI_DEVFN(11, 0), 4);
+ pci_bus_set_register_mem_fn(bus, vpb_register_mem, vpb_unregister_mem, s);
/* ??? Register memory space. */
diff --git a/hw/vga-pci.c b/hw/vga-pci.c
index 68fbe36..bd78c92 100644
--- a/hw/vga-pci.c
+++ b/hw/vga-pci.c
@@ -79,7 +79,7 @@ static int pci_vga_initfn(PCIDevice *dev)
// vga + console init
vga_common_init(s, VGA_RAM_SIZE);
- vga_init(s, -1);
+ vga_init(s, 0);
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
--
1.6.2.4
