On Sat, 2016-07-09 at 12:46 +1000, Benjamin Herrenschmidt wrote: > On Sat, 2016-07-09 at 01:43 +0100, Mark Cave-Ayland wrote: > > On 01/07/16 07:41, David Gibson wrote: > > > > > From: Benjamin Herrenschmidt > > > > > > The architecture specifies that any instruction that sets MSR:PR > > > will also > > > set MSR:EE, IR and DR. > > .../... > > > Unfortunately this patch causes a regression and breaks booting OS > > 9 and > > OS X under qemu-system-ppc. > > Any idea what is breaking specifically ? The architecture is pretty > clear > here, could it be that they rely on old implementations allowing the > incorrect combination ? > > Maybe we can make the restriction 64-bit server only...
Additionally, hreg_compute_mem_idx() will treat PR=1 as DR=1/IR=1 as well ! That means that if those old processors allow PR=1 and IR or DR=0 and MacOS uses it, we do have a TLB coherency problem in qemu. Cheers, Ben.
