On 06/23/2016 04:15 AM, Andrew Jeffery wrote: > The SCU is a collection of chip-level control registers that manage the > various functions supported by ASPEED SoCs. Typically the bits control > interactions with clocks, external hardware or reset behaviour, and we > can largly take a hands-off approach to reads and writes. > > Firmware makes heavy use of the state to determine how to boot, but the > reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev > property is exposed so that the integrating SoC model can configure the > silicon revision, which in-turn selects the appropriate reset values. > Further qdev properties are exposed so the board model can configure the > board-dependent hardware strapping. > > Almost all provided AST2400 reset values are specified by the datasheet. > The notable exception is SOC_SCRATCH1, where we mark the DRAM as > successfully initialised to avoid unnecessary dark corners in the SoC's > u-boot support. > > Signed-off-by: Andrew Jeffery <and...@aj.id.au>
Reviewed-by: Cédric Le Goater <c...@kaod.org> Thanks, C.
