On 20 June 2016 at 15:05, Timothy Pearson <kb9...@pearsoncomputing.net> wrote: > I mostly filed the bug report since I was seeing multiple different > attempts to implement this, and even a proper patch series on the > mailing list, but no movement at all toward integrating this feature > into mainline qemu. > > What would be needed to e.g. make the patch series on the mailing list > acceptable for merge?
The bare minimum is that things need to not break for any guest x host combination. The RFC patchset from Kirill says that it doesn't work for all ARM guest code, for instance. It also needs to fall back cleanly if the backend doesn't support vector ops, and I'm not sure if the RFC does that. It needs to implement more than a single test "vector add". It needs to be reasonably demonstrated that it's actually a win on real-life code rather than a trivial microbenchmark. The various concerns listed in the RFC cover letter need to be discussed and addressed. This is all certainly doable, but the missing thing is "nobody is actually doing it", not "we didn't know about this". An RFC patchset is a sketch of a design, and there's a long way between that and committable code. The ACM paper looks like a classic example of a bit of academic work: maybe they did something interesting, but their intended end output was a paper, not code, and they never submitted any patches to us that I'm aware of. (And again, "academic prototype" and "production code" are often far apart.) thanks -- PMM -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1594069 Title: SIMD instructions translated to scalar host instructions Status in QEMU: Confirmed Bug description: SIMD instructions inside the guest (NEON, MMX, SSE, SSE2, AVX) are translated to scalar instructions on the host instead of SIMD instructions. It appears that there have been a few efforts to rectify this [1], and even a submitted patch series, but all discussion has effectively died out [2]. I would like to see better SIMD performance on qemu, especially as non-x86 architectures are becoming widely used (e.g. ARM). [1] http://dl.acm.org/citation.cfm?id=2757098&dl=ACM&coll=DL&CFID=633095244&CFTOKEN=12352103 [2] https://lists.nongnu.org/archive/html/qemu-devel/2014-10/msg01720.html To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1594069/+subscriptions
