On Wed, Jun 15, 2016 at 07:19:39AM +1000, Benjamin Herrenschmidt wrote: > On Tue, 2016-06-14 at 16:25 +1000, David Gibson wrote: > > > Properly implement LPES0/1 handling for HV vs. !HV mode. > > > > > > Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> > > > [clg: AIL implementation was fixed in commit 5c94b2a5e5ef > > > fixed checkpatch.pl errors ] > > > > Code looks ok, but the short description really needs an update, > > since > > this has been taken out of its original series context. > > This is still what this does. It properly implements support for LPCR0 > (LPCR1 isn't supported). It also fixes how the HV bit is handled when > taking interrupts and which set of SRR's are used in some cases.
It's the "Rework POWER7 & POWER8 exception model (part 2)" bit which
is the problem.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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