On 3 June 2016 at 18:15, Sergey Sorokin <afaral...@yandex.ru> wrote:
> Address size is 40-bit for the AArch32 stage 2 translation,
> and t0sz can be negative (from -8 to 7),
> so we need to adjust it to use the existing TTBR selecting logic.
>
> Signed-off-by: Sergey Sorokin <afaral...@yandex.ru>
> ---
> target-arm/helper.c | 38 ++++++++++++++++++++++----------------
> @@ -7348,15 +7354,15 @@ static bool get_phys_addr_lpae(CPUARMState *env,
> target_ulong address,
> }
> }
> t1sz = extract32(tcr->raw_tcr, 16, 6);
> - if (va_size == 64) {
> + if (aarch64) {
> t1sz = MIN(t1sz, 39);
> t1sz = MAX(t1sz, 16);
> }
I wonder if we should move the extraction of t1sz into the preceding
if() -- then we could do the '3 bit field vs 6 bit field' thing the way
we do for t0sz. Still, that's a cleanup for a different patch.
Applied to target-arm.next, thanks.
-- PMM
