On Thu, Apr 21, 2016 at 08:24:41AM -0700, Hollis Blanchard wrote: > These are obviously critical to understanding interrupt delivery: > gic_enable_irq > gic_disable_irq > gic_set_irq (inbound irq from device models) > gic_update_set_irq (outbound irq to CPU) > gic_acknowledge_irq > > The only one that I think might raise eyebrows is gic_update_bestirq, but I've > (sadly) debugged problems that ended up being caused by unexpected priorities. > Knowing that the GIC has an irq ready, but doesn't deliver to the CPU due to > priority, has also proven important. > > Signed-off-by: Hollis Blanchard <hollis_blanch...@mentor.com> > --- > hw/intc/arm_gic.c | 12 ++++++++++++ > trace-events | 8 ++++++++ > 2 files changed, 20 insertions(+)
Thanks, applied to my tracing tree (for QEMU 2.7): https://github.com/stefanha/qemu/commits/tracing Stefan
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