On Fri, Jun 04, 2010 at 12:14:27PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/s390/tcg-target.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
> tcg/s390/tcg-target.h | 4 ++--
> 2 files changed, 48 insertions(+), 2 deletions(-)
This patch looks fine.
> diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
> index 3a98ca3..f53038b 100644
> --- a/tcg/s390/tcg-target.c
> +++ b/tcg/s390/tcg-target.c
> @@ -108,6 +108,8 @@ typedef enum S390Opcode {
> RR_SR = 0x1b,
> RR_XR = 0x17,
>
> + RSY_RLL = 0xeb1d,
> + RSY_RLLG = 0xeb1c,
> RSY_SLLG = 0xeb0d,
> RSY_SRAG = 0xeb0a,
> RSY_SRLG = 0xeb0c,
> @@ -1201,6 +1203,44 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
> opc,
> op = RSY_SRAG;
> goto do_shift64;
>
> + case INDEX_op_rotl_i32:
> + /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol.
> */
> + if (const_args[2]) {
> + tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE,
> args[2]);
> + } else {
> + tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0);
> + }
> + break;
> + case INDEX_op_rotr_i32:
> + if (const_args[2]) {
> + tcg_out_sh64(s, RSY_RLL, args[0], args[1],
> + TCG_REG_NONE, (32 - args[2]) & 31);
> + } else {
> + tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
> + tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0);
> + }
> + break;
> +
> + case INDEX_op_rotl_i64:
> + if (const_args[2]) {
> + tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
> + TCG_REG_NONE, args[2]);
> + } else {
> + tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0);
> + }
> + break;
> + case INDEX_op_rotr_i64:
> + if (const_args[2]) {
> + tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
> + TCG_REG_NONE, (64 - args[2]) & 63);
> + } else {
> + /* We can use the smaller 32-bit negate because only the
> + low 6 bits are examined for the rotate. */
> + tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
> + tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0);
> + }
> + break;
> +
> case INDEX_op_ext8s_i32:
> tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]);
> break;
> @@ -1365,6 +1405,9 @@ static const TCGTargetOpDef s390_op_defs[] = {
> { INDEX_op_shr_i32, { "r", "0", "Ri" } },
> { INDEX_op_sar_i32, { "r", "0", "Ri" } },
>
> + { INDEX_op_rotl_i32, { "r", "r", "Ri" } },
> + { INDEX_op_rotr_i32, { "r", "r", "Ri" } },
> +
> { INDEX_op_ext8s_i32, { "r", "r" } },
> { INDEX_op_ext8u_i32, { "r", "r" } },
> { INDEX_op_ext16s_i32, { "r", "r" } },
> @@ -1423,6 +1466,9 @@ static const TCGTargetOpDef s390_op_defs[] = {
> { INDEX_op_shr_i64, { "r", "r", "Ri" } },
> { INDEX_op_sar_i64, { "r", "r", "Ri" } },
>
> + { INDEX_op_rotl_i64, { "r", "r", "Ri" } },
> + { INDEX_op_rotr_i64, { "r", "r", "Ri" } },
> +
> { INDEX_op_ext8s_i64, { "r", "r" } },
> { INDEX_op_ext8u_i64, { "r", "r" } },
> { INDEX_op_ext16s_i64, { "r", "r" } },
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index dcb9bc3..9135c7a 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -49,7 +49,7 @@ typedef enum TCGReg {
>
> /* optional instructions */
> #define TCG_TARGET_HAS_div2_i32
> -// #define TCG_TARGET_HAS_rot_i32
> +#define TCG_TARGET_HAS_rot_i32
> #define TCG_TARGET_HAS_ext8s_i32
> #define TCG_TARGET_HAS_ext16s_i32
> #define TCG_TARGET_HAS_ext8u_i32
> @@ -65,7 +65,7 @@ typedef enum TCGReg {
> // #define TCG_TARGET_HAS_nor_i32
>
> #define TCG_TARGET_HAS_div2_i64
> -// #define TCG_TARGET_HAS_rot_i64
> +#define TCG_TARGET_HAS_rot_i64
> #define TCG_TARGET_HAS_ext8s_i64
> #define TCG_TARGET_HAS_ext16s_i64
> #define TCG_TARGET_HAS_ext32s_i64
> --
> 1.7.0.1
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net
