On 19 February 2016 at 13:40, Sergey Fedorov <serge.f...@gmail.com> wrote:
> On 19.02.2016 14:26, Peter Maydell wrote:
>> Implement the performance monitor register traps controlled
>> by MDCR_EL3.TPM and MDCR_EL2.TPM. Most of the performance
>> registers already have an access function to deal with the
>> user-enable bit, and the TPM checks can be added there. We
>> also need a new access function which only implements the
>> TPM checks for use by the few not-EL0-accessible registers
>> and by PMUSERENR_EL0 (which is always EL0-readable).
>>
>> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
>> +/* Check for traps to performance monitor registers, which are controlled
>> + * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
>> + */
>> +static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
>> + bool isread)
>> +{
>> + int el = arm_current_el(env);
>> +
>> + if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
>> + && !arm_is_secure_below_el3(env)) {
>> + return CP_ACCESS_TRAP_EL2;
>> + }
>> + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
>> + return CP_ACCESS_TRAP_EL3;
>
> This trap is only possible if EL3 is using AArch64.
You mean, we shouldn't honour the bit if EL3 is AArch32?
I guess that's true of the other MDCR_EL3 bits too (in the
32-bit SDER those bits are RES0). Probably it would be
better to implement a write function for SDCR that didn't
allow setting of reserved bits.
thanks
-- PMM
