The HMP command "info registers" produces somewhat different information on
different ppc cpu variants. For those with a hash MMU it's supposed to
include the SDR1, DAR and DSISR registers related to the MMU. However,
the switch is missing a couple of MMU model variants, meaning we will
miss out this information on certain CPUs which should have it.
This patch corrects the oversight. (Really these MMU model IDs need a big
cleanup, but we might as well fix the bug in the interim).
Signed-off-by: David Gibson <da...@gibson.dropbear.id.au>
---
target-ppc/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 0057bda..287d679 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11352,7 +11352,9 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
case POWERPC_MMU_64B:
case POWERPC_MMU_2_03:
case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_07:
+ case POWERPC_MMU_2_07a:
#endif
cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
" DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
--
2.5.0
