On Sat, Jan 23, 2016 at 09:40:10PM +0100, Hervé Poussineau wrote: > We currently don't emulate the I2C bus provided by CUDA.
The MOL source has the comment /* this reply is important on B&W G3 */ in the CUDA_COMBINED_FORMAT_IIC case (differentiating it from the general 0x2 error case); any idea if that's relevant? (0x5 is an SRQ error? I guess it would also be nice to add constants for all these magic numbers.) - Alyssa
