On Sun, Jan 17, 2016 at 11:12 PM, Peter Crosthwaite
<crosthwaitepe...@gmail.com> wrote:
> From: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
>
> There is a CPU data endianness test that is used to drive the
> virtio_big_endian test.
>
> Move this up to the header so it can be more generally used for endian
> tests. The KVM specific cpu_syncronize_state call is left behind in the
> virtio specific function.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
Reviewed-by: Alistair Francis <alistair.fran...@xilinx.com>
Also, I'm not too sure what the appropriate action is here, but this
is still signed off by your Xilinx address.
Thanks,
Alistair
> ---
>
> target-arm/cpu.c | 19 +++----------------
> target-arm/cpu.h | 19 +++++++++++++++++++
> 2 files changed, 22 insertions(+), 16 deletions(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 35a1f12..d3b73bf 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -368,26 +368,13 @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq,
> int level)
> #endif
> }
>
> -static bool arm_cpu_is_big_endian(CPUState *cs)
> +static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
> {
> ARMCPU *cpu = ARM_CPU(cs);
> CPUARMState *env = &cpu->env;
> - int cur_el;
>
> cpu_synchronize_state(cs);
> -
> - /* In 32bit guest endianness is determined by looking at CPSR's E bit */
> - if (!is_a64(env)) {
> - return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
> - }
> -
> - cur_el = arm_current_el(env);
> -
> - if (cur_el == 0) {
> - return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
> - }
> -
> - return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
> + return arm_cpu_is_big_endian(env);
> }
>
> #endif
> @@ -1420,7 +1407,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void
> *data)
> cc->do_unaligned_access = arm_cpu_do_unaligned_access;
> cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
> cc->vmsd = &vmstate_arm_cpu;
> - cc->virtio_is_big_endian = arm_cpu_is_big_endian;
> + cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
> #endif
> cc->gdb_num_core_regs = 26;
> cc->gdb_core_xml_file = "arm-core.xml";
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index f83070a..54675c7 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -1795,6 +1795,25 @@ static inline bool arm_singlestep_active(CPUARMState
> *env)
> && arm_generate_debug_exceptions(env);
> }
>
> +/* Return true if the processor is in big-endian mode. */
> +static bool arm_cpu_is_big_endian(CPUARMState *env)
> +{
> + int cur_el;
> +
> + /* In 32bit endianness is determined by looking at CPSR's E bit */
> + if (!is_a64(env)) {
> + return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
> + }
> +
> + cur_el = arm_current_el(env);
> +
> + if (cur_el == 0) {
> + return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
> + }
> +
> + return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
> +}
> +
> #include "exec/cpu-all.h"
>
> /* Bit usage in the TB flags field: bit 31 indicates whether we are
> --
> 1.9.1
>
>
