Hi, > From: qemu-devel-bounces+andrew.baumann=microsoft....@nongnu.org > [mailto:qemu-devel- > bounces+andrew.baumann=microsoft....@nongnu.org] On Behalf Of > Alvise Rigo > Sent: Monday, 14 December 2015 00:41 > > This is the sixth iteration of the patch series which applies to the > upstream branch of QEMU (v2.5.0-rc3). > > Changes versus previous versions are at the bottom of this cover letter. > > The code is also available at following repository: > https://git.virtualopensystems.com/dev/qemu-mt.git > branch: > slowpath-for-atomic-v6-no-mttcg > > This patch series provides an infrastructure for atomic instruction > implementation in QEMU, thus offering a 'legacy' solution for > translating guest atomic instructions. Moreover, it can be considered as > a first step toward a multi-thread TCG. > > The underlying idea is to provide new TCG helpers (sort of softmmu > helpers) that guarantee atomicity to some memory accesses or in general > a way to define memory transactions. > > More specifically, the new softmmu helpers behave as LoadLink and > StoreConditional instructions, and are called from TCG code by means of > target specific helpers. This work includes the implementation for all > the ARM atomic instructions, see target-arm/op_helper.c.
As a heads up, we just added support for alignment checks in LDREX: https://github.com/qemu/qemu/commit/30901475b91ef1f46304404ab4bfe89097f61b96 Hopefully it is an easy change to ensure that the same check happens for the relevant loads when CONFIG_TCG_USE_LDST_EXCL is enabled? Thanks, Andrew
