For sig == 0 case, the original implementation is incorrect (although it
passes gcc testsuite), it needs to consider about sign for float_zero.
The related fix diff for it is below. After patches v5 are finished
reviewing, I shall merge the fix diff below to patch v6, next.
Thanks.
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index dba8566..5ad8bb5 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -7098,19 +7098,15 @@ float32 normalize_roundpack_float32(flag sign,
int_fast16_t exp, uint32_t sig,
return packFloat32(sign, 0, sig);
}
+ if (!sig) {
+ return float32_set_sign(float32_zero, sign);
+ }
+
if (sign) {
if (sig & 0x7FFFFFFF) {
return normalizeRoundAndPackFloat32(1, exp - 2, sig, status);
}
- if (sig) {
- return packFloat32(1, exp, 0);
- } else {
- return float32_zero;
- }
- }
-
- if (!sig) {
- return float32_zero;
+ return packFloat32(1, exp, 0);
}
scount = countLeadingZeros64(absa) - 40;
On 1/3/16 06:25, cheng...@emindsoft.com.cn wrote:
> From: Chen Gang <gang.chen.5...@gmail.com>
>
> It is based on (u)int32_to_float32 function to support float32 packing.
>
> Signed-off-by: Chen Gang <gang.chen.5...@gmail.com>
> ---
> fpu/softfloat.c | 55
> +++++++++++++++++++++++++++++++++++++++++++++++++
> include/fpu/softfloat.h | 8 +++++++
> 2 files changed, 63 insertions(+)
>
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index f1170fe..dba8566 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -7080,6 +7080,61 @@ float64 uint32_to_float64(uint32_t a, float_status
> *status)
> return int64_to_float64(a, status);
> }
>
> +/*
> + * The mantissa contents the hide bit, e.g. exp: 0x9e with sig: 1 means 1.0f.
> + *
> + * It references from int32_to_float32() and uint32_to_float32()
> + */
> +float32 normalize_roundpack_float32(flag sign, int_fast16_t exp, uint32_t
> sig,
> + float_status *status)
> +{
> + uint64_t absa = sig;
> + int8_t scount;
> +
> + if (exp >= 0xff) {
> + return packFloat32(sign, 0xFF, 0);
> + } else if (exp <= 0) {
> + shift32RightJamming(sig, 0 - exp, &sig);
> + return packFloat32(sign, 0, sig);
> + }
> +
> + if (sign) {
> + if (sig & 0x7FFFFFFF) {
> + return normalizeRoundAndPackFloat32(1, exp - 2, sig, status);
> + }
> + if (sig) {
> + return packFloat32(1, exp, 0);
> + } else {
> + return float32_zero;
> + }
> + }
> +
> + if (!sig) {
> + return float32_zero;
> + }
> +
> + scount = countLeadingZeros64(absa) - 40;
> + if (scount >= 0) {
> + exp -= 7 + scount + 2;
> + if (exp <= 0) {
> + return packFloat32(0, 0, absa);
> + }
> + return packFloat32(0, exp, absa << scount);
> + }
> +
> + scount += 7;
> + exp -= scount + 2;
> + if (exp <= 0) {
> + return packFloat32(0, 0, absa);
> + }
> + if (scount < 0) {
> + shift64RightJamming(absa, 0 - scount, &absa);
> + } else {
> + absa <<= scount;
> + }
> + return roundAndPackFloat32(0, exp, absa, status);
> +}
> +
> uint32 float32_to_uint32(float32 a, float_status *status)
> {
> int64_t v;
> diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
> index ded34eb..4995a15 100644
> --- a/include/fpu/softfloat.h
> +++ b/include/fpu/softfloat.h
> @@ -422,6 +422,14 @@ int float32_is_signaling_nan( float32 );
> float32 float32_maybe_silence_nan( float32 );
> float32 float32_scalbn(float32, int, float_status *status);
>
> +/*
> + * The mantissa contents the hide bit, e.g. exp: 0x9e with sig: 1 means 1.0f.
> + *
> + * It references from int32_to_float32() and uint32_to_float32()
> + */
> +float32 normalize_roundpack_float32(flag sign, int_fast16_t exp, uint32_t
> sig,
> + float_status *status);
> +
> static inline float32 float32_abs(float32 a)
> {
> /* Note that abs does *not* handle NaN specially, nor does
>
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
