On 27/11/2015 11:29, Alexander Graf wrote: > > We rework the way the MMU indices are calculated, providing separate > > indices for I and D side based on MSR:IR and MSR:DR respectively, > > and thus no longer need to flush the TLB on context changes. This also > > adds correct support for HV as a separate address space. > > > > Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> > > Paolo had a patch set poking at the same places a while back to speed up > the ppc target by almost 10%. > > Paolo, what happened to those patches? Would you prefer to rebase them > on top of the HV bits or have Ben look into them while he's at it anyway? ;)
Ben decided to do it this way, which avoids a proliferation of MMU modes. The net effect of his patches is the same if not better. Paolo
