Place device reported PCI capabilities at the same offsets as placed by
the VMware virtual hardware:
Express Endpoint at [40], MSI at [7c]
Signed-off-by: Shmulik Ladkani <shmulik.ladk...@ravellosystems.com>
---
hw/scsi/vmw_pvscsi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index 8854fd9..5c8cae1 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -32,7 +32,8 @@
#include "trace.h"
-#define PVSCSI_MSI_OFFSET (0x50)
+#define PVSCSI_EXP_EP_OFFSET (0x40)
+#define PVSCSI_MSI_OFFSET (0x7c)
#define PVSCSI_USE_64BIT (true)
#define PVSCSI_PER_VECTOR_MASK (false)
@@ -1082,7 +1083,7 @@ pvscsi_init(PCIDevice *pci_dev)
pvscsi_init_msi(s);
if (pci_bus_is_express(pci_dev->bus)) {
- pcie_endpoint_cap_init(pci_dev, 0);
+ pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET);
}
s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
--
1.9.1
