On Wed, Oct 28, 2015 at 12:10 AM, Jean-Christophe DUBOIS <j...@tribudubois.net> wrote: > Le 27/10/2015 23:41, Peter Crosthwaite a écrit : > > > > On Tue, Oct 27, 2015 at 3:32 PM, Jean-Christophe Dubois > <j...@tribudubois.net> wrote: >> >> The i.MX6 GPIO device supports 2 interrupts instead of one. >> >> * 1 for the lower 16 GPIOs. >> * 1 for the upper 16 GPIOs. >> >> i.MX31 and i.MX25 only support 1 interrupt for the 32 GPIOs. >> > > So an architectural question, is it the case that the IP always has two > outbound interrupt lines but MX31 and 25 always OR together on the SoC > level? > > > Well, I am not part of Freescale so I just don't know anything about > internal implementation details of this IP and its use inside the SOC. > > What we can say is that the dual interrupt version (i.MX6) is newer than the > single one (i.MX31, i.MX25). So my guess is that this is an evolution of the > IP and the goal was to make GPIO interrupt handling easier, faster and > prioritisable. > > > > If that is the case I think it would be cleaner to do on the board level. > > > At the SOC level I was planning to set (or not) the new property and to > assign 1 (or 2) IRQ to the device. >
Ok, there were no architecture clues in the TRM so this approach wins. Reviewed-by: Peter Crosthwaite <crosthwaite.pe...@gmail.com> One possibility is to do some lightweight subclasses for the imx25/31 and imx6 versions, to avoid SoCs having to manipulate number properties for fixed IPs. See hw/usb/hcd-ehci-sysbus.c for some examples of SoCs tweaking a peripheral to get their own version of it as a customized device type. Regards, Peter > Regards > > JC > > > > Regards, > Peter > > >> >> So we add a property to turn the behavior on when required. >> >> Signed-off-by: Jean-Christophe Dubois <j...@tribudubois.net> >> uint32_t isr; >> bool has_edge_sel; >> uint32_t edge_sel; >> + bool has_upper_pin_irq; >> >> - qemu_irq irq; >> + qemu_irq irq[2]; >> qemu_irq output[IMX_GPIO_PIN_COUNT]; >> } IMXGPIOState; >> >> -- >> 2.5.0 >> > >
