Hi Michael
Thanks for your quick response
On 10/27/2015 05:47 PM, Michael S. Tsirkin wrote:
On Tue, Oct 27, 2015 at 05:39:01PM +0800, Cao jin wrote:
static
bool pcie_has_upstream_port(PCIDevice *dev)
{
PCIDevice *parent_dev = pci_bridge_get_device(pci_dev->bus);
/*
* Device associated with an upstream port.
* As there are several types of these, it's easier to check the
* parent device: upstream ports are always connected to
* root or downstream ports.
*/
return parent_dev &&
pci_is_express(parent_dev) &&
parent_dev->exp.exp_cap &&
(pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
}
Assume my understanding is right, which means both ARI and non-ARI device
have the upstream port(root port or downstream port), could the existence of
upstream port be the judgment condition?
This tells us whether we are behind a port that
can address devices in slot != 0.
Seems I find something, according to spec: Endpoints are classified as
either legacy, PCI Express, or Root Complex Integrated Endpoints. I think
this is also what you means in comment "As there are several types of these"
And "we are behind a port" means the device is not a Root Complex
Integrated, only the other two types can be behind a port.
Am I right about this?
No, device can be a bridge itself.
Ah yes, you are saying a PCIe-->PCI(PCI-X) bridge, right?
It's simple: root and downstream
ports only have 1 slot (and it's a physical one) so you know there's
always 1 device there. It could have multiple functions.
Yes, I am aware.
It seems there is no big and obvious error about other understandings in
last mail:) I just want to get myself totally understood about ARI and
your implementation before using your code. Thank you very much for your
time and patience:)
And the v6 is on the way
--
Yours Sincerely,
Cao Jin
